A receiving device including a data transmission interface in which data (packet) and a clock are transmitted in parallel, generally, includes a clock data recovery (CDR) and a phase locked loop (PLL). The CDR reproduces a first clock from received data. The PLL generates a second clock that is acquired by multiplying received clock by N.
It is desired that the power consumption of a receiving device including a CDR and a PLL is reduced, and the lock-up time of the CDR and the PLL is shortened.